Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design
نویسندگان
چکیده
منابع مشابه
Low-Power Adder Design for Nano-Scale CMOS
A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.
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ژورنال
عنوان ژورنال: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
سال: 2016
ISSN: 1063-8210,1557-9999
DOI: 10.1109/tvlsi.2015.2438233